Many approaches have been used for the layout of various types of network switching and communication chips. Prior chip layout schemes have not, however, been suited to accommodating the operation and extremely high switching speeds and other quite different characteristics of the above-mentioned Chatter, universal multi-port internally cached DRAM bank operation. In such, wherein there is provided a switching module logic control for connecting any of the I/O resources through serial interfaces with any I/O resource buffer competing for access to a common bus under a dynamic configuration of switching allocation appropriate for the desired data routability among the interfaces--with the switching module assigning any buffer to any serial interface and without any intermediate step of data transfer--prior chip layout schemes have not been suited to accommodating this operation and the extremely high switching speeds attainable therewith. The common bus access competition may be with an external competing CPU or similar control data ports, if used, competing for common system bus access with the I/O data resources serially interfaced with the internally cached DRAMs, sometimes referred to as "macros", and/or the competition of the I/O resource data buffers themselves for access to a common internal line bus within the DRAM bank, as described in said patent.